One of the fastest-growing chip packaging technologies last year and this year is wafer-level packaging (WLP), primarily because of its smaller size, lower power needs, inherently lower cost, and better electrical characteristics.
Process steps for all types of WLP are performed on the wafer, not on the separate, finished chip. The main constraint in this technology is the number of I/Os that can be placed under the chip and still be routable on the board. In wafer-level chip-scale packaging (WLCSP), the package's outline is smaller than the chip, not larger, as it is in most other packaging types.
WLP and WLCSP are being used today in a variety of applications, including passives, MEMS, image sensors, and the embedding of active ICs in mobile communications devices. In both CCD and CMOS image sensors, WLP techniques are used for encapsulation of a glass wafer. According to the 2007 International Technology Roadmap for Semiconductors (ITRS), stacked-die WLCSP techniques are packaging not only memory and standard logic chips, but also RF devices for Bluetooth, Wi-Fi and GPS communications. Automotive applications are also a main driver of WLP's growth.
Challenges in WLP designs include increasing package performance and functionality while reducing power, size and cost, which is leading to more complex single- and multi-die packages. Traditionally, the basic fan-in WLP design has been a technology suited for smaller die and lower pin counts, typically 40 to 50 pins per package. But as demand has increased for WLP's benefits, especially from designers of handheld consumer devices, package I/O counts are rising well above 100 pins.
Higher I/O counts are being driven by wireless chips that integrate multiple types of RF circuits - such as Bluetooth, FM radios, TV tuners, and GPS units - on a single large die. Designers are now aiming at 200 I/Os for WLPs, but achieving reliability at that level will be a major challenge. The 2007 ITRS predicts that 200 pins will appear first in memory chip packages in 2009.
Pitch is also becoming finer, decreasing over the last few years from
0.5mm to 0.4mm, with demand pushing for an even finer 0.3mm.
Reliability is a concern here, too, because smaller pitch is
accompanied by smaller solder
balls, which can affect structural integrity.
To cope
with issues caused by larger die, WLCSP designs are being improved with
various structures that help to counter stress and increase
reliability, such as underfill in board-level assemblies and
stress-absorbing layers and bump structures.
Three basic methods can be used to manufacture WLPs. For some types of MEMS, including RF MEMS and resonators that need environmental and mechanical protection, packagers use wafer capping methods. Wafers can also be stacked in WLPs, or WLPs can simply be formed as an "SMT-ready" package.
Stacked WLPs are a major enabler of 3D packaging. In fact, there's a thin line between the two and a lot of overlap, and the distinction is becoming fuzzier with time. When wafers are stacked, then connected together with, for example, through-silicon vias (TSV), and then cut, the result is usually considered an example of 3D packaging, although the actual packaging is done at the wafer level.
Some industry observers think that, as demand for smaller packages with higher I/Os continues to rise, WLP will gradually replace older package technologies, such as leadframes and BGAs. The 2007 ITRS lists several changes needed for WLP technology to meet requirements in the future. Those at the top of the list include reduced processing temperatures, integrating passives in RDLs, and integrating RF shielding with power shielding.
Difficult challenges include the mechanical tolerances required for aligning chips to small pads, contacts on small pads, multi-layer RDL topology, on-chip cross-talk, and yield and defect repair issues in embedded WLPs.
by Ann R. Thryft
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