System-on-chip (SoC) design, integrating high frequency switching DC-DC converter directly on the same IC, with digital control circuits and sensitive analog circuits, provides effective power management circuits with reduced bulk and weight for portable devices. However, the high frequency switching DC-DC converter introduces large power/ground bounce and substrate noise, which can greatly degrade the performance of the analog circuits integrated on the same chip.
Using traditional circuit simulation methods, the chip substrate is treated as a single ground node. The generation, propagation and isolation of the substrate noise and its effect on circuit characterization cannot be simulated.
This article discusses how Cadence's QRC helps to investigate the mechanisms of noise injection for the DC-DC converter and their effects on sensitive analog blocks by extracting the parasitic resistance and capacitance of the substrate from the layout, and identify which isolation strategies are effective. Optimization methods to speed up the substrate extraction using the tool are also discussed.
Simulations and experiments have been carried out to prove that the high frequency switching DC-DC converter circuit introduces huge substrate noise, which can be decreased significantly by the optimization of the schematic or layout design, such as by merging NWELL, adding PEPI, and using separated PADs for less noisy blocks. Layout-based substrate noise simulation work using QRC is said to help analyze and predict the effects of different substrate noise reduction techniques. The work suggests that QRC has good application for power designs with large size power devices.
by Jian Yang, Tommy Mao, Iven Zheng, Hongwei Zhao, Richard Wang, Freescale Semiconductor (China) Ltd
Full article:
http://techon.nikkeibp.co.jp/NEA/solutions/0901002.pdf
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