Nikkei Electronics Asia -- October 2008
Solutions
Mass Imaging for Ultra-Miniaturized Electronics

Sept 25, 2008 16:53 Nikkei Electronics Asia

Emerging component package styles increase utilization of board space, but manufacturers need to understand how to configure assembly processes including screen printing to achieve commercially viable yield and throughput.

Shrinking I/O and connector pitches, consolidation of board-level interconnects using technologies such as via-in pad, and reduction in standard SMD form factors through 0201 to the emergence of 01005 are some examples of the ingenuity applied to all levels of assembly.

But manufacturers need to be able to work with these technologies as part of an inline, automated progression towards the end-of-line, to achieve efficient production at high rates of yield and throughput. Since the indicators for end-of-line yield are set at pre-placement, it is important to understand how the accepted screen printing practices must change, if at all, to accommodate the latest package styles and board design techniques. 

Recent work has analyzed the impact of 0.3mm-pitch CSPs, as well as SMD resistors in the new 01005 EIA form factor, on printing processes including printer set-up, stencil design, and solder paste formulation. The 0.3mm CSP represents a major evolution within the SMT arena. This device will require arrays of mass imaged solder paste at pitches and volumes that only a few short years ago would have warranted a semiconductor classification.

Challenges include sub-seven-second cycle times employed in surface-mount production, the thin, often uneven FR4 boards generally used in SMT, and the standard working environments of a typical assembly operation. By comparison, semiconductor packaging processes have the benefits of much slower cycle times, perfectly flat wafers, and clean-room environments.

by Jeff Schake, Clive Ashmore,
DEK International

Full article:
http://techon.nikkeibp.co.jp/NEA/solutions/0810002.pdf

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