On July 17 and 18, Cadence Design Systems Japan held the DA Show/CDN Live! Japan 2008, a private event, in Tokyo. A number of interesting presentations were made, two of which are described below.
Using Formal VerifiersMasahide Ochiai, engineering leader, Tokyo Digital Design, Worldwide Development at Texas Instruments Japan Ltd, reported on formal verification through property checks, as performed at Texas Instruments Inc (TI) of the US design sites worldwide, including TI Japan. He explained that TI has been using property checks for formal verification for about six years in the US, implementing it in TI design sites in Japan, France, India and elsewhere about three years ago. At present, TI uses the Incisive Formal Verifier (IFV) from Cadence Design Systems.
The firm made the decision to install formal verifiers at TI sites worldwide because they can handle comprehensive verification. Verification is implemented at a very early stage in integrated circuit (IC) development, thereby helping prevent the need to start over after a problem is discovered downstream. Formal verification does have problems, though, he added, because the content to be checked must be described as assertions.
To resolve this problem, TI has adopted a policy of using formal verifiers as extensively as possible, as long as the designer does not need to describe assertions. In general, there are two methods. The first is to use the assertions provided by the EDA vendor, and the second is for the designer to enter verification items into a spreadsheet (Excel, etc) and use dedicated software to convert that data into assertions.
According to TI Japan's Ochiai, this conversion software was developed by Cadence Design Systems and by TI in the past. Conversion software developed by Cadence Design Systems, TI India, TI France and elsewhere was introduced, along with a discussion of its effects and other points. For example, IFV was used to generate assertions for the intellectual property (IP) core for design for testability (DFT) developed by TI France, reducing verification to only eight hours. The logic simulation used previously took 1.5 weeks to run.
Dr Toshiki Kanamoto, senior engineer, Physical Verification & Extraction Technology Development Group, SIP & Analog EDA Technology Development Dept, Design Technology Div, LSI Product Technology Unit at Renesas Technology Corp of Japan discussed the application of a layout parasitic parameter extraction EDA system in a power metal-oxide semiconductor field effect transistor (MOSFET) mid-signal IC. The EDA system was developed from the QRC Extraction tool for layout parameter extraction (LPE) from Cadence Design Systems.
Until now, there have been no LPE tools for power MOSFET optimization, so in most cases a prototype had to be made and measured, representing a considerable investment of time and capital.
Renesas Technology worked with Cadence Design Systems to add a function for large-current operation to the QRC Extraction LPE tool for small-signal operation ICs, making it possible to use on power MOSFETs. The target layout, connected power MOSFET and other circuit elements are divided into small portions. QRC Extraction is applied to each portion, and a parameter network constructed for the extracted data for use as the layout parameter.
by Ikutaro Kojima
Nikkei Electronics |
Nikkei Monozukuri |
Nikkei Automotive Technology |
|---|---|---|
 |
 |
 |
| The magazine for electronics designers and managers. | Design You Won't Regret - How to Reduce the Risk of Accidents | The comprehensive automotive technology magazine. |
Copyright © 1995-2010 Nikkei Business Publications, Inc. All rights reserved.
All editorial content and graphics on this Web site may not be reproduced in whole or in part without the express permission of the copyright owner.
