Nikkei Electronics Asia -- October 2008
Cover Story
FPGAs Leveling with ASICs, ASSPs

Now that design rules have stopped shrinking for ASICs, ASSPs and the like, they seem likely to be replaced by FPGAs. With their design rules coming into the 40nm generation, FPGAs will soon be level with ASICs and ASSPs in terms of circuit size and performance.

There's a barrier to the semiconductor design rule at the 90nm generation. We are currently using 120nm-generation manufacturing technology for 32-bit automotive microcontrollers, but at the development level the manufacturing technology ranges from 40nm to 90nm. Even so, we don't expect to see much design rule shrink in the near future," said a source at Toyota Motor Corp of Japan. This complaint is becoming increasingly common among semiconductor users. 

The major reason that semiconductor users are beginning to say they don't really need finer rules is that there has been a sharp rise in development costs for application-specific integrated circuits (ASIC), application-specific standard products (ASSP) and other ICs as rules have shrunk. Until now, ASICs, ASSPs, etc, have been mostly cell-based ICs, which means a development cost of about Yen100 million for a 90nm rule chip. When the technology drops to 65nm, cost doubles to about Yen200 million. The primary cost driver is the expense for the mask set used to form the semiconductor circuits. 

45nm-generation ASICs, which entered production in the fall of 2007 at a few advanced manufacturers, are heading for a development cost of about Yen300 million, according to multiple semiconductor manufacturers.
If an IC costing that much to develop only sold 100,000 chips, for example, the per-IC development
cost would work out to Yen3,000. As price plunges continue in digital household appliances and products of all types, there are very few applications that can afford this development cost.

The slowdown in rule shrink in cell-based ICs is evident in the breakdown of ASIC design quantities by rule (Fig 1). In 2002 the most common design rule for ASICs was 180nm, accounting for 38% of the total. In 2003 it was 130nm, at 37%, but the speed of generation change slacked off abruptly. In 2007, 130nm still accounted for 27% of total ASIC designs, followed by 90nm at 23% and 180nm at 14%.

The situation seems unlikely to change much in the future: forecasts indicate that 130nm and 90nm ASICs will be the most common in 2011, each accounting for 24% of the total. Brand-new 65nm chips will only account for 15%.

FPGAs: Companion Chips

Now that design rules have stopped shrinking for ASICs, ASSPs and the like, they seem likely to be replaced by field-programmable gate arrays (FPGA; Fig 2). The circuit configuration of FPGAs can be freely revised by equipment manufacturers on the spot, which means that they have no need to pay development costs, including mask sets. Even better, FPGAs do not require any circuit fabrication after design, which means faster equipment development. In other words, they effectively avoid the microfabrication problems faced by ASICs, ASSPs, etc. 

FPGAs have been widely used for many years in applications such as prototyping and verification. They have been mounted in volume-production products for infrastructural communications equipment, for example, and began appearing in some consumer electronics products a few years ago.

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