Nikkei Electronics Asia -- March 2008
Analysis
Spin Injection MRAM Main Focus at MMM

R&D into non-volatile MRAM is picking up. At the 52nd Annual Conference on Magnetism & Magnetic Materials (MMM), MRAM products grabbed the limelight, particularly those with potential for use in cars and mobile phones.

We can see how to get down to the 30nm generation - probably down to even the 20nm generation, technically. Development is already committed to replacing DRAM," revealed a source at a major domestic semiconductor manufacturer.

Non-volatile magnetic random access memory (MRAM), based on the magneto-resistance effect, has been in the doldrums for years, but has suddenly taken on new life. The development of MRAM using the spin injection magnetization reversal technique, a brand new principle of operation, is picking up speed at semiconductor manufacturers in Japan and overseas (Fig 1). The renewed interest by memory manufacturers was clearly evident at the 52nd Annual Conference on Magnetism & Magnetic Materials (MMM), held November 2007 in Florida, the US.

At the MMM 2007 Conference, several technologies were proposed to manufacture spin injection MRAM using 45nm to 32nm generation process technology, and reduce memory cell area to the same level as that of dynamic RAM (DRAM), or 6F2 to 8F2 (where F is the minimum feature size). Target applications include replacing merged memory in automotive microcontrollers and similar chips, multi-chip packages (MCP) for mobile phones, single DRAM chips and single NOR Flash memory chips.

Attendees were especially interested in efforts to apply vertical magnetization technology, now making such a contribution in boosting the density of hard disk drives (HDD), to spin injection MRAM. Toshiba Corp of Japan has become the first in the world to apply vertical magnetization technology to spin injection MRAM, based on a tunneling magnetoresistive (TMR) device, and National Institute of Advanced Industrial Science & Technology (AIST) also presented a giant magnetoresistive (GMR) device based on vertical magnetization technology.

Papers describing refinements in technologies using conventional planar magnetization also drew crowds, apparently offering a better chance of practical development over MRAM utilizing cutting-edge vertical magnetization technology. For example, Hitachi Ltd of Japan and Tohoku University of Japan are working on improving the laminated Ferri structure used to enhance thermal stability and other characteristics in the spin injection MRAMs they are jointly developing.

The magnetoresistive (MR) ratio of TMR devices is also rising, in the hope of speeding up read and write times and other characteristics in spin injection MRAMs. The joint Hitachi-Tohoku University group announced a TMR device with an MR ratio of 500% at room temperature.

MRAM Problems Solved
Spin injection MRAMs represent a revolutionary technology for the MRAM industry, which has been toiling away for so long.

MRAM made its initial appearance in about 2000, heralded as a leading candidate for the "ultimate memory." It became apparent, however, that the shifts to small geometry and larger capacity were not going to happen as hoped. Products in volume production now are still 180nm-generation technology, with capacities of 4-Mbit, limiting applications to replacing battery-backed static RAM (SRAM) and other niches.

Spin injection MRAM may well shatter these barriers and grab a major share of the market, however, because in addition to simplifying the shift toward smaller features, it also makes it easier to boost memory capacity.

The basic principle of operation, namely magnetic field write, has been behind the difficulties MRAM chips have been having in reducing line widths and boosting capacity (Fig 1a). In magnetic field write, the magnetic field created by the combination of the bit line current and the write/word line cause magnetic reversal in the TMR device free layer.

The write current needed to cause magnetic reversal is inversely proportional to the volume of the magnetic body, which means write current increases as line width decreases. Cell transistors with high drive capacity are needed to handle the high current, which leads to expanded cell area. Worse, because a write/word line is also needed, the theoretical cell area is 12F2, or 1.5x to 2x the size of DRAMs.

The spin injection design resolves these problems. Instead of using writing data with a magnetic field, current is directly input to the TMR device to reverse its free layer magnetization (Fig 1b). The threshold current needed to reverse magnetization drops with line width, and because no write/word line is needed the theoretical memory cell area drops to about the same level as that of DRAMs, at 6F2 to 8F2.

First Applications
Spin injection MRAMs have an excellent chance of winning a major market in the future because they combine the functional advantages of existing memories like DRAM and NAND Flash with performance superior to most (Table 1). Spin injection MRAM has the same non-volatile functionality as Flash memory, in that information is retained even when power is cut off; but MRAM also offers the random access functionality of DRAM. When it comes to performance, spin injection MRAM has fast read/write, only 2ns to 20ns. MRAMs do not require the erase process demanded by Flash memory, and write time is several orders of magnitude faster than with Flash memory. Even considering that the read/write times for DRAM, generally one of the faster memory types, are 30ns to 50ns, the outstanding performance of spin injection MRAM stands out. Even better, it can handle 1015 rewrites, a major improvement over the (approximate) 105 of Flash memory, and on a par with memory technologies like DRAM and SRAM.

Spin injection MRAMs are superior to existing types of memory in many ways, including function and performance, and they may replace a number of types of memory currently used in equipment (Fig 2). If the development of constituent technology continues smoothly,

MRAMs will probably spread into the market in two stages. The first is as a replacement for merged memory in automotive microcontrollers and similar applications, and the second is as a replacement for mobile phone MCPs, single DRAMs and single NOR Flash memory, among others.

Most of the technical hurdles that need to be cleared for the first stage are already pretty well cleared. Most automotive microcontrollers have internal SRAM for working memory and internal Flash memory for program storage. If spin injection MRAM is integrated into the microcontroller it would be possible to replace both the other memories.

Major microcontroller users are ready to switch to spin injection MRAMs if the conditions are right. Masayuki Hattori, project general manager, Multimedia Group, BR Automotive Software Engineering Dept., Toyota Tokyo Technical Center at Toyota Motor Corp of Japan, for example, said, "The Flash memory used in automotive microcontrollers now has a low number of rewrites, and we really want faster read/write performance than Flash memory can provide. MRAMs are assured for more rewrites, and have superior performance, or so we have heard. As long as the cost is comparable, there's no reason not to switch to MRAMs."

It is possible that volume production of 65nm-generation spin injection MRAMs could begin as early as 2008 or 2009, as a replacement for the merged memory in automotive microcontrollers. Grandis Inc of the US, respected by Toshiba and other players in the industry as the firm with the most advanced technology in spin injection MRAM using planar magnetization in the world, predicts, "For applications like replacing merged memory in microcontrollers, it should be possible to make spin injection MRAMs using 65nm minimum features to achieve a memory cell area of 20F2 to 30F2. And it will probably enter commercial use fairly rapidly." While the firm hasn't released any details, it has probably already solved most of the technical issues in the way of commercial application, and is expected to begin volume production in 2008.

Two Requirements...
Two conditions will have to be met before MRAMs can achieve the second stage, namely, replacing mobile phone multi-chip packages (MCP), stand-alone DRAM and NOR Flash memory and the like. The first is that memory cell area will have to be reduced to 6F2 to 8F2, on a par with single DRAM and NOR Flash memory. The second is that the technology will have to be capable of application at 45nm to 32nm, and beyond.

Many of the technologies proposed at the MMM Conference are designed to fulfill both of these requirements. The adoption of vertical magnetization in spin injection MRAM attracted particular interest from those attending. As a source from a major domestic semiconductor manufacturer pointed out, "It is quite possible that cell area can be reduced to only 6F2 or 8F2, and manufacR&D into non-volatile MRAM is picking up. At the 52nd Annual Conference on Magnetism & Magnetic Materials (MMM), MRAM products grabbed the limelight, particularly those with potential for use in cars and mobile phones.
turing technology might go as low as about 20nm."

Papers were presented on spin injection MRAMs using vertical magnetization by Toshiba and AIST, Toshiba using a TMR device and AIST a GMR device.

Toshiba claims to be the first in the world to report on a TMR device in vertical magnetization. As the name indicates, with vertical magnetization, the magnetic layer is magnetized in the vertical dimension, and consequently much less energy is required for magnetic reversal than for planar magnetization, which means data can be written with lower current. The lower current makes it easier to shrink the selection transistors in the cells.

Another reason Toshiba is so interested in vertical magnetization is that it is easier to both shrink cell area and improve thermal stability simultaneously, even though the two characteristics are generally in a trade-off relationship. If thermal stability is low it increases the chance that a transition will occur between the low-low and high-low resistance states due to a rise in ambient temperature. That would degrade data retention when no read current is present, and tend to increase write errors when inputting read current. The device would be useless as memory.

By utilizing vertical magnetization, as Toshiba explained, "It is possible to achieve an aspect ratio of 1 in the horizontal direction for the TMR device. That means we can use, for example, a circular TMR device. With an aspect ratio of 1 it becomes a lot easier to use the minimum feature size in cell fabrication, and that's why we can cut the cell area to only 6F2 or 8F2."

With conventional planar magnetization, TMR devices with aspect ratios of 1.6 or 2, for example, are used to improve thermal stability. That means if the short side is defined as a unit length of "1", the adjoining side must be set to a length of 1.6 or 2, or as needed to match the ratio being used. "This makes it much harder to work at the minimum feature size during memory cell fabrication, so it is that much harder to keep cell area down to 6F2 or 8F2," explained Toshiba.

Thermal Agitation: 100
Vertical magnetization makes it possible to reduce cell area down to 6F2 o 8F2 while also improving thermal stability. Thermal agitation is a commonly-used index of thermal stability, and can be defined as =MsHkV/2kT, where the free layer saturation magnetization is Ms, anistotropic magnetic field Hk, free layer volume V, Boltzmann constant k and temperature T.

Commercial application of spin injection MRAMs will require a thermal agitation of at least 60, and the higher the better. V drops with line width, which means that even if =60 can be achieved in a given generation, it will become impossible to maintain it as geometry shrinks. The larger thermal agitation, the easier it is to handle ever-smaller line widths.

Ms (saturation) is defined by the material, and V is largely dependent on cell area, which means that in most cases spin injection MRAMs using planar magnetization have increased Hk in order to increase thermal agitation. The most common method of increasing Hk has been to use a longitudinal TMR device.

With vertical magnetization, as one domestic semiconductor manufacturer pointed out, "Hk can be quite high, regardless of the shape of the TMR device." This characteristic of vertical magnetization has been known for some time, but until now it has been extremely difficult to achieve the flatness needed for the film interface constituting the TMR device and other components, making it almost impossible to apply vertical magnetization to MRAMs.

Toshiba revamped materials, processes and other elements based on the basic principles of operation of spin injection and vertical magnetization, and worked on improving the device structure especially at the interface so important in ensuring performance. Rare earth-based TbCoFe was used in both free and pinned layers, MgO in the tunnel isolation film and CoFeB in the interface film, all thinned down to about 1nm. Interfaces were very tight thanks to extremely flat films. Researchers have already verified that the resulting device operates stably, and exhibits excellent magnetic reversal repeatability. The thermal agitation is high, at 100. The switching current density, which is closely related to memory cell area, is low at 3 x 106A/cm2, and coercive strength high at about 1.2kOe.

Toshiba intends to develop new materials appropriate for spin injection, and technologies to further reduce the variation in characteristics, which is crucial in large-scale integration. The constituent technologies are expected to be combined within a few years to establish a solid base technology.

AIST's CPP GMR Device
AIST presented a paper on vertical magnetization technology utilizing a current perpendicular to plane (CPP) GMR device. In this device the sensing current is perpendicular to the film plane.

Fe/Pt was used for both free and pinned layers, with an Au spacer. Vertical magnetization was used for the free and pinned layers. In both layers, the Fe/Pt multi-layered film was formed by alternating single atoms of Fe and Pt, formed by molecular beam epitaxy (MBE). The single-atom stacking approach resulted in an extremely thin free layer, only 1nm to 2nm thick.

The thinner free layer made it possible to reduce switching current. While switching current density is about three times that of Toshiba, at 1 x 107A/cm2, a source at AIST commented, "We will be able to cut switching current density by an order of magnitude by replacing the GMR device with a TMR device." Thermal agitation is said to be over 60.

by Motoyuki Oishi

Websites:
AIST: www.aist.go.jp
Grandis: www.grandisinc.com
Hitachi: www.hitachi.com
Tohoku University: www.tohoku.ac.jp
Toshiba: www.toshiba.com
Toyota Motor: www.toyota.co.jp/en

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