Nikkei Electronics Asia -- January 2008
Analysis
DRAM Makers Cut Cost by 30% a Year to 2011

"We will reduce memory cell area to 4F2 from the 40nm-generation DRAM entering volume production in about 2011," said the director, chief technical officer (CTO), Technology Development Office, Takao Adachi of Elpida Memory Inc of Japan at the Industry Strategy & Technology Forum (ISTF) 2007 seminar held in September 2007. His statement astonished many in the audience (Fig 1).
Most dynamic random access memory (DRAM) memory cells have areas of 8F2, where F is the minimum feature, but the most commonly used cell technology is expected to shift to 6F2 in 2007 to 2008. Elpida Memory was the first firm in the world to disclose plans to put 4F2 memory cell technology into commercial use. The latest (2006) version of the International Technology Roadmap for Semiconductors (ITRS), drawn up by representatives from the top semiconductor manufacturers in the world to sketch out the future of the industry through 2020, makes no mention of 4F2 DRAM cell technology by then.
A manufacturing engineer at a major Korean DRAM manufacturer believes that Adachi's comment "...demonstrates his commitment to maintaining a cost reduction rate of 30% annually until 4F2 memory cells can be achieved, in spite of widespread pessimism about 4F2 technology." Trial calculations of memory cell area based on the ITRS indicate that while it will shrink at an annual rate of 30% from 2005 through 2008, the pace will slacken off to 20% annually from 2009 (Fig 1). If 4F2 memory cells can be achieved in 2011 with 40nm manufacturing technology, as planned by Elpida Memory, it will raise the possibility of maintaining the 30% annual rate through at least 2011. With 4F2 cells, it becomes possible to use the same manufacturing technology generation as 6F2, but shrink the cell area by a third, and this will support an annual reduction of 30% in DRAM cost through 2011.

Dual Approach
The technologies being used to reduce DRAM cost are changing from smaller design rules only to a combination of design rules with improved cell layout. Until now it has been possible to maintain an annual reduction in DRAM manufacturing cost of 30% by merely adopting new manufacturing technologies supporting smaller design rules. From about 2004, though, since the minimum feature dropped to 100nm, it has been increasingly difficult to maintain this pace merely by shrinking the rule. As a result, DRAM manufacturers are working to reduce cell area by adopting new cell layouts.
A number of manufacturers will adopt 6F2 memory cells in full-scale production of chips in 2007 and 2008 (Fig 2). Compared to 8F2 cells, this represents a 20% reduction in DRAM chip area. Even with 6F2 cells, though, as a source at Micron Technology Inc of the US explained, "Performance, dissipation, reliability and other key specs are the same as the old cells."
Multiple manufacturers are already volume producing 6F2 cell DRAM, following in the wake of Micron Technology (Fig 3), which spearheaded commercial adoption. The firm first adopted the technology in about 2002, and began volume production of a DRAM using 6F2 78nm-generation technology from the fall of 2006. Samsung Electronics Co Ltd of Korea was next, launching a 68nm-generation DRAM chip using 6F2 cells from the first half of 2007. As from the end of 2007 through the second quarter of 2008, Elpida Memory is beginning volume production of 65nm-technology 6F2 cell DRAM, mostly in a 1-Gbit spec.

Resolving Noise Issue
Manufacturers are adopting the open bit-line architecture to make 6F2 cell area possible. This reduces cell area by placing a capacitor at every intersection between a word line and a bit line (Fig 2b). The open bit-line architecture has not been possible until now because memory cells have been too susceptible to noise. The 8F2 cell evaded the problem by using a folded bit-line architecture (Fig 2a).
A sense amp must be used to detect the minute voltage output from the DRAM cell, referenced to the potential of the reference bit line. The folded bit-line architecture places the reference bit line adjacent to the cell in question, so that even if the cell being read is effected by noise, the reference potential will be effected by the same noise, minimizing the danger of a read error. In open bit-line DRAM the reference bit line is separate from the memory cell, and exposed to a different noise environment.
The open bit-line memory cell has finally become possible thanks to more robust DRAM internal circuits. Read current has increased because of the reduction in cell parasitic resistance due to the smaller cell area, reduced rear resistance provided by the use of metal top electrodes on capacitors, and other design improvements. As a result, the relative effects of noise have dropped.

4F2 Cell Technologies
After 6F2 cells come 4F2 cells. No manufacturer has solved all the obstacles to commercial adoption yet, but all appear to be evaluating possible technologies. A number of technologies seem to offer ways of achieving 4F2 cell areas. Samsung Electronics, the top firm in DRAM chips, believes that technologies like vertical transistors and stacking multiple cells on a single Si wafer are the most promising.
The former idea, vertical transistors, is a technology to construct the cell transistor channel vertically (Fig 4). A vertical channel is formed at each intersection between word and bit lines, and surrounded by the gate dielectric (Fig 4a). The capacitors are formed directly above the channels, making it possible to reduce cell area to 4F2 (Fig 4b).
The latter technology, stacked cells, achieves 4F2 by merely stacking two 8F2 cells. No firms, however, including Samsung Electronics, have presented any papers on stacking DRAM cells, although Samsung Electronics has published results of cell transistor stacking in other types of chip, including NAND Flash memory and static random access memory (SRAM). Research into SRAM appears to be the farthest along, with memory array prototypes already completed. The SRAMs used in cell phones and similar equipment today are quite large, with cell areas of 84F2. Samsung Electronics has stacked the transistors formerly arranged in a single plane, reducing a 6-transistor cell to only 25F2.
The technical barriers to DRAM cell stacking, however, are formidable. While it is enough to just stack transistors for SRAM, NAND and the like, DRAM also demands that capacitors be stacked.

Transistor Improvement
In order to continue shrinking manufacturing technology, industry will have to resolve a few key issues, like reducing the prices of photolith systems and improving cell transistor technology. As the design rule shrinks, cell transistor channels grow shorter, and the short-channel effect means an increase in off-current. That in turn requires a refresh cycle even shorter than the 64ms used in DRAM now, which presents a significant load for users.
To assure a certain minimum on-current (which directly affects performance) while suppressing off-current, DRAM manufacturers have begun to change the fundamental cell transistor architecture. Until lately, channels were formed in the same plane at the Si wafer, but now they are being made with 3D technology. Samsung Electronics, for example, began using recess channel array transistors (RCAT) in its DRAM chips from the 90nm or 80nm generation designs (Fig 5). Holes are cut into the Si wafer, coated with gate dielectric and then filled with poly-Si. Channels are formed along these holes, providing longer effective channels while shortening them within the plane. This makes it easier to control off-current.
According to a source at Samsung Electronics, RCAT will have to be further improved for use at 70nm and below (Fig 6). If the RCAT structure is merely reduced in size, the radius of curvature at the end of the hole would degrade gate voltage input efficiency.
To improve the gate voltage input efficiency, Samsung Electronics has developed the sphere-shaped recess channel array transistor (S-RCAT), with a spherical end. This was partially adopted from 80nm chips, and is scheduled to be introduced across the board from 70nm-generation DRAMs.
The firm is considering another change to RCAT in the 60nm generation. Reducing S-RCAT in size would tend to allow electrical fields to accumulate at the boundary between sphere and hole, and could degrade reliability of the gate dielectric. Samsung Electronics hopes to avoid this by using a U-shaped recess channel array transistor (U-RCAT). Changing from a sphere to a U-shaped design alleviates charge accumulation, and improves gate dielectric reliability.

by Motoyuki Oishi

Websites:
Elpida Memory: www.elpida.com/en
Micron Technology: www.microntech.com
Samsung Electronics: www.samsung.com

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