Nikkei Electronics Asia -- September 2007
Insights
Verification Challenges Facing Analog, RF Designers

Analog and RF blocks are critical in today's SoCs for consumer, wireless, computer, and networking applications. The stringent performance requirements on these analog/RF blocks require the support of very high frequencies or I/O speeds, the management of difficult noise environments and the support of complex wireless/wireline communication protocol requirements. The verification of these blocks prior to tape out is a significant challenge for design teams. Existing
verification flows have not kept pace with the design complexity and, as a result, design teams now face multi-week and multi-month verification times for full analog/RF subsystems.

In many cases, the verification process is fraught with convergence and accuracy issues. As a result, designers use overly conservative design approaches, perform less optimization, lengthen schedules for verification, and take calculated risks. This makes analog/RF verification the leading cause of delays in volume production of these ICs. Traditional SPICE simulators are therefore no longer enough. In order to break this bottleneck, delivery of new verification functionality and faster verification speed and capacity - with no loss of SPICE accuracy - is required. This article reviews the problems faced in analog/ RF verification in today's SoCs in consumer, wireless, computer, and networking applications and discusses how verification technology has helped semiconductor companies to dramatically reduce the time to ramp to volume production.

Analog, RF Verification Challenges
Today's design teams have established a SPICE-simulation-based verification flow that works well for small analog/RF blocks. However, the complexity of analog/RF blocks is growing at a very rapid pace, driven by both the integration of analog functionality into SoCs and the growth in new functionality requirements in the portable wireless and media-player markets. The traditional verification flow used for small analog RF blocks does not work for these large and complex analog /RF circuits. Simulations take multiple days to weeks, and in many cases, do not converge at all.

Analog circuits have grown from hundreds of devices to well over 100K devices. Designs are now hierarchical and multi-block, often integrating passive devices on the same substrate. Simulators need to have the performance and capacity to handle these full-circuit simulations. Circuit frequencies have moved from the MHz to multiple-GHz range for common devices. Periodic analysis is becoming a requirement for many high-speed analog applications. Simulators need to handle transient and periodic analysis that demonstrate good correlation with silicon results.

In addition, RF circuits have moved to predominantly multi-frequency operation with frequencies that are orders-of-magnitude apart. Examples include transceiver ICs with integrated VCOs, high-ratio dividers and mixers. Simulators therefore must perform efficient transient analysis for circuits with multiple greatly dissimilar frequencies.

Process technology evolution for analog is another reason for the increased verification issues. Analog and RF circuits have moved from specialized micron-scale processes (e.g. bipolar) to CMOS nanometer-scale processes. At nanometer-scales, inter- and intra-die process variations greatly affect circuit performance characteristics and yield. Auto-calibration helps, but at the cost of additional complexity and area. Simulators need full-SPICE accuracy and high performance for extensive corner and Monte Carlo analysis on reasonable-sized circuits.

In these high-performance and complex implementations, wiring and the board environment dramatically affects performance at GHz frequencies, especially in nanometer-scale CMOS processes. Parasitics are required to verify sensitive blocks and their interconnections into the surrounding environment. Simulators also need the full-SPICE performance and capacity to handle post-layout parasitic verification, including effects of board traces, for multi-block circuits.

Finally, noise due to inherent device sources such as thermal and flicker, as well as other circuitry (digital, analog, and RF) has now emerged to become a first-order effect. The performance of critical analog and RF building blocks, such as ADCs, VCOs, and PLLs can change dramatically due to the impact of noise from devices. Simulators therefore must provide silicon-accurate intrinsic and extrinsic analysis including random and deterministic noise sources.

Limitations of Traditional Simulators
A leading complaint heard from design teams today is that the traditional SPICE simulation flow that works well for small analog/RF blocks is no longer sufficient for complex blocks and full-circuit verification. For small blocks, designers rely on transistor-level SPICE simulation with full accuracy to verify their small blocks. They run tasks such as circuit simulation, post-layout simulation, variation analysis (corners, Monte Carlo), including package inductance and transmission line effects, noise analysis (deterministic, thermal, flicker) and RF periodic analysis. These simulations help ensure performance and functionality and greatly reduce the risk of non-working silicon for small blocks.

However, as designers try to run the same full-accuracy simulation tasks on large designs they simply cannot get the job completed. Transient analysis with traditional SPICE simulator on a large analog block such as a PLL or a multi-channel DC-DC converter can take several days to several weeks. In addition, in many instances, these simulators have great difficulty in achieving DC convergence.

Digital FastSPICE simulators are alternatives for large digital designs, but they do not address the big analog/RF verification challenge. FastSPICE simulators get their speedup by using simplified assumptions and approximations which sacrifice accuracy that is essential to analog and RF applications.

As a result of the large block verification challenge, designers end up using overly conservative design approaches, perform less optimization, lengthen schedules for verification and take calculated risks of their chips not working. This makes analog/RF verification the leading cause of delays in volume production of these ICs.

Advanced Verification Tool
The precision circuit analysis tools have shown that they have the ability to solve these complex verification problems which traditional analog/RF verification tools cannot handle. The technology combines innovative applied mathematics with advanced numerical optimization techniques. The technology was developed from the bottom-up where accuracy has not been compromised. Among the new core components are an efficient stiff differential algebraic equation solver, a non-linear stochastic analysis engine, a fast sparse matrix solver, globally convergent nonlinear solvers, and an unified time-domain/frequency-domain analysis engine. The result is full-SPICE-accurate transient and periodic analysis that is 5-10x faster than SPICE.

Unlike digital FastSPICE simulators, the precision circuit analysis technology makes no simplified assumptions or approximations. It instead solves the original device equations on the original circuit with accuracy that is equivalent to or exceeds that of SPICE simulators. This means that it needs no block-level tuning and always provides full-accuracy at every node in the circuit; hence every simulation is a full performance simulation.

Circuit design teams from some consumer, wireless, computer, and networking companies have validated the technology versus silicon on several hundred production designs from 0.5um down to 45nm. The results of full-SPICE accuracy transient performance for a representative set of circuits is shown in Table 1.

The circuits range two orders-of-magnitude in complexity, the applications include full wireless transceivers, complex analog/mixed-signal ICs, and consumer ICs. All of these are production designs with the original testbench and circuit setup. They are all out-of-the-box results, meaning that the user did not tune the simulator algorithms or perform block-level tuning. In each case, the original circuit designer compared critical waveforms and node-specific measurements with their current SPICE simulator results and validated that PCA provided full-SPICE accuracy.

Analog and RF blocks are critical in today's SoCs for consumer, wireless, computer, and networking applications. In these applications, if the analog is late, the chip is late. The verification of these blocks prior to tape out is a significant challenge for design teams. Existing verification flows have not kept pace with the design complexity and, as a result, design teams now face multi-week and multi-month verification times for full analog/RF subsystems. Traditional SPICE is no longer enough and new tools such as the precision circuit analysis tools have demonstrated the ability to break the bottleneck and solve these complex verification problems.

by Ravi Subramanian,
Ph.D, President & CEO,
Berkeley Design Automation Inc

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