Nikkei Electronics Asia -- February 2007
Tech Analysis
Chip-on-Chip Offers Higher Memory Capacity, Speed

Chip-on-chip (CoC) semiconductor packaging technology offers high performance at low cost for a range of equipment, including digital household appliances, mobile gear, servers and routers.

A new chip-on-chip (CoC) semiconductor packaging technology has been developed, offering high performance at low cost for a wide range of equipment including digital household appliances, mobile gear, servers and routers. CoC makes it possible to put large-capacity memory, like 512-Mbit or 1-Gbit, into the same package at the logic integrated circuit (IC). The data transfer rate between them is high, from several Gbps to several hundred Gbps.
Until now, mounting memory and logic in the same package has required a system-on-chip (SoC) using dynamic random access memory (DRAM) technology, or a system-in-package (SiP) solution connecting the chips to each other with wire bonding. Each approach has its own advantages and disadvantages, but it has been difficult to achieve both large-capacity memory and high-speed data transfer between memory and logic. CoC packaging, however, fulfills both demands simultaneously with a manufacturing cost significantly lower than merged DRAM.

Commercial Use
CoC packaging seems likely to make great strides in commercial use in 2007. Renesas Technology Corp of Japan was planning to adopt the technology in products in the fourth quarter of 2006, and NEC Electronics Corp of Japan in the first quarter of 2007. Both firms plan to offer CoC technology as one of their packages manufactured in-house.
Fabless memory manufacturer System Fabrication Technologies Inc of Japan is expected to use CoC technology in digital household appliances in 2007. Sony Corp of Japan began volume production in 2005, but has no plans for sale to the merchandise market.

Interconnect via Bumps
It is possible to achieve both large-capacity memory and high-speed data transfer with CoC technology because the memory chip is stacked with the logic IC, interconnected to each other with microbumps (Table 1). Individual memory chips are used, essentially eliminating the memory capacity limitations of merged DRAM. The higher data transfer rate is made possible by the greater bitwidth, achieved by a larger quantity of microbumps. The microbumps are in an array, providing more interconnects than wire bonding, and because they are only several dozen um in diameter they offer low parasitic capacitance, resistance, inductance and other characteristics, making it easier to raise the operating frequency.
This architecture actually takes the best features of merged DRAM SoCs and wire-bond SiPs for more than memory capacity and data transfer rate, however. Dissipation, for example, is lower than that of wire-bond SiPs, at about the same level as merged DRAM SoCs.
Bump interconnect does have its own problems, though: with CoC, only two chips can be stacked. Many memory chip manufacturers position chips next to each other in the plane, holding a maximum of three. Still, most people in the field don't view this as a major obstacle. The capacity of memory used extensively in SiPs is 512-Mbit, and this can be easily provided by a single memory chip. Existing CoC technology can utilize DRAM up through 1-Gbit in capacity already.
CoC can't use standard memory chips, either, because the pin assignments are different. The manufacturing process itself is identical, though, so the cost increase is minimal.

Overcoming Limitations
One of the reasons that CoC is suddenly entering commercial use is that the limitations of conventional approaches like merged DRAM SoCs and SiPs are becoming apparent. The capacity of memory integrated into merged DRAM SoCs, for example, is no more than 128-Mbit, and will probably not exceed 256-Mbit even if the design rule is reduced down to 65nm. While it is technically possible to use larger memory capacities with the technology, most engineers agree that cost would be prohibitive.
Equipment, unfortunately, is demanding ever-larger amounts of memory. A digital high-definition television (HDTV), for example, used to get by with 64-Mbit or less of memory, but systems supporting 1080p imagery now come with 128-Mbit to 256-Mbit.
As long as performance and function continue to improve in equipment, it will mean steadily increasing memory capacity, and eventually merged DRAM will be unable to handle the requirements.
Now that the limits to merged DRAM are becoming obvious, manufacturers who have concentrated on merged DRAM in the past are suddenly very interested in CoC. Sony Computer Entertainment Inc of Japan recently switched from merged DRAM to CoC for its PlayStation Portable (PSP) game system. "Through the PlayStation 2 we positioned merged DRAM SoCs as a core competence of the Sony semiconductor effort, but as performance rose and new functions were added, merged DRAM SoCs simply couldn't handle it any more," explained Tohru Ogawa, general manager, System in Package Technology Development Department, Semiconductor Technology Development Group, Semiconductor Business Unit at Sony.
SiPs, where chips are connected by wire bonding, have difficulty providing the data transfer rates demanded by high-speed DRAM. Wire-bond SiPs, said Masaya Kawano, manager, 3D-LSI, Package Technology Development Group, Advanced Device Development Division, Technology Foundation Development Op Unit of NEC Electronics, "...are barely able to handle DDR2, not even 1Gbps." Again, it is not technically impossible to achieve a data rate of several Gbps with wire bonding, but as Kawano added, "Designing chips for 1Gbps or above is quite difficult." The interfaces for general-purpose DRAM are getting faster and faster, and wire bonding for inter-chip connection will just not be able to keep up in the near future.

Speed, Footprint, etc
There are a number of different approaches to CoC, in terms of the final characteristics, pin count, mounting footprint and other points, and manufacturers must choose the optimal one for the specific application. The CoC technologies in use recently can be broken down into three major groups (Fig 1): mobile equipment, digital household appliances, and high-performance equipment like servers.
Each developing manufacturer is aiming at a different application (Table 2). NEC Electronics and Sony are developing CoC for use in mobile equipment, with about 500 external pins per chip. Sony, System Fabrication Technologies and others are working on CoC for non-mobile equipment like digital household appliances, also with about 500 external pins but generally with larger footprints than designs for mobile application.
Renesas Technology is interested in CoC for use in communications equipment such as servers and routers, with about 2,000 external pins per chip. It also offers chips with 500 to 700 pins for use in office document stations and other applications

Size of Wafer-Level CSP
NEC Electronics has the technology to make CoC packages for mobile equipment especially small, achieving a size close to that of wafer-level chip-scale packages (CSP). The package mounting area is almost the same as the memory chip footprint. NEC Electronics has dubbed the technology smart chip connection with feedthrough interposer (SMAFTI).
At present only one memory chip and one logic chip can be stacked together. With about 500 external pins there would seem to be plenty of potential applications, but the package footprint actually allows up to about 1,000 pins.
The outstanding characteristic of this method is that it is appropriate for applications where the memory chip footprint is larger than that of the logic IC. In mobile equipment there are many cases where diverse functions are implemented in software, making it common for the memory chip to be larger than the logic chip. This is why NEC Electronics proposed an internal architecture most effective for large memory chips. It can also be used in the reverse case, but it would cost a bit more.
Concretely, the memory chip is packaged like a wafer-level CSP, with no plastic interposer. The logic IC is then mounted in the center of the memory chip face with the interconnection electrodes. When the finished package is mounted on the printed circuit board, the logic chip is sandwiched between the memory and the board.
NEC Electronics uses microbumps to connect the memory chip and the logic IC, across a feedthrough interposer (FTI). The FTI is used to make it possible to feed the logic IC power lead directly outside the package, without passing through the memory chip. This is done because if the logic IC power lead is connected to the memory power lead, the high resistance can cause the logic IC supply voltage to drop below permissible levels. When the logic IC is smaller than the memory this problem has to be resolved somehow, and different firms are developing their own solutions.
The NEC Electronics method totally eliminates wire bonding from inside the package, and compared to solutions handled with wire bonding, this means that its packages will handle higher operating frequencies for interfaces with systems outside the package.

Combining Wire Bonding
Sony is developing another CoC implementation for mobile equipment, but with a slightly larger mounting footprint. Compared to the NEC Electronics concept, it eliminates restrictions imposed by the relative sizes of the memory chip and the logic IC. Sony currently has no plans to make the technology available outside the company, but applications where logic is larger than memory would probably benefit from using their approach.
The method can be used not only with ball grid arrays (BGA), but also with quad flat packs (QFP) and other packages. The same type of package can be used in digital household appliances and other large systems as well as in mobile gear. Sony has dubbed the technology the Multichip LSI (MCL).
The Sony CoC architecture is simple. The wiring surfaces of the logic IC and memory chip are positioned face-to-face, with the smaller chip mounted on the larger one. Terminals around the periphery of the larger chip are connected to external pins via interposers, leadframes or something else. Sony uses wire bonding to connect the chip, interposer etc, which means there may be some delays in external signal swapping.
When the logic ICs have small footprints and are mounted on top of the memory chip, the Sony approach requires some modification in the form of creating a dedicated power supply lead in the memory chip for the logic IC. Depending on the permissible range for logic IC supply voltage, it could mean a new, low-resistance rewiring layer in the memory chip, which avoids the problem mentioned above.
In general, memory chip cost rises when a technology such as a low-resistance rewiring layer not used in DRAM manufacturing is required. According to Sony's Ogawa, "For large-scale production runs of a million chips a month or more, we expect to be able to drop the price to about the same level as general-purpose DRAM, even for memory requiring special wiring."

Usable with Up to 4 Chips
System Fabrication Technologies has developed technology for non-mobile equipment, such as digital household appliances (Fig 2). The firm's solution eliminates any problem with the relative size of logic ICs and memory chips, and has excellent thermal radiation performance because multiple chips can be mounted in the same package. The memory and
logic chips are mounted next to each other on a silicon interposer in a technology the firm calls System in Silicon (SiS).
Up to four chips can be mounted in one package, but the more chips there are, the larger the Si interposer and the higher the cost. In practical terms it works best with three chips: one logic and two memory. Sony has said it can also make test samples with the same architecture.
Compared to other methods, however, the chip-to-chip data transfer rate is difficult to increase. The operating frequency is relatively low, at 33MHz or 66MHz, for example, and the data rate tops out at several dozen Gbps. This is because of the Si interposer used to connect the chips, increasing the line length. Compared to the microbump interconnect architecture, where the line length is several dozen um, this method has distances of several mm. In addition, wire bonding is used to connect the Si interposer to external pins, further dropping the external data transfer rate.

Up to 2,000 External Pins
Renesas Technology is developing CoC for use in servers, routers and similar applications, supporting up to about 2,000 external pins. The logic IC is assumed to be larger than the memory chip, for high-performance equipment. As Michitaka Kimura, group manager, Advanced Package Development Group, Jisso Technology Development Div, Production & Technology Unit, at the company explained, "Logic chips for servers and similar equipment are generally larger than memory chips, and our solution addresses that specifically." If the memory chip is larger, the firm's technology, which it calls CoC flip-chip BGA (COC-FCBGA), can't be used.
The external data transfer rate is high, and the method uses no wire bonding inside the package. Solder balls are used to connect the chip to the plastic interposer, which connects to external pins. Renesas Technology's CoC implementation resembles the firm's FC-BGA package already in use for servers and similar equipment, which uses flip-chip mounting to place the logic IC on the plastic interposer. For CoC, the memory chip is inserted between them.

by Mayuko Uno

Websites:
NEC Electronics: www.necel.com
Renesas Technology: www.renesas.com
Sony: www.sony.com
System Fabrication Technologies: www.s-f-t.co.jp

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