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Single-Chip Solution Combines Boot, Data Storage Capabilities
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While NAND technology is said to be superior to NOR technology for data storage, it has to be accompanied by another Flash device for booting purposes; thus, two Flash devices are always necessary. M-Systems, Inc has designed a 16-bit, 32-Mbyte NAND Flash disk solution - DiskOnChip Millennium Plus - that combines boot with data storage capabilities into one single chip. To better understand the uniqueness of the solution, let's take a look at the major differences between NAND and the most common Flash technology, NOR as well as the traditional booting sequence of a computer system.
What is Flash Memory?
Flash memory is a type of constantly powered non-volatile memory that can be erased and reprogrammed in units of memory called blocks. It got its name because the microchip is organized so that a section of memory cells is erased in a single action, or Flash. Flash is actually a variation of the EEPROM with much faster updating speed.
The most common Flash types are NOR and NAND and they can be differentiated from each other by the mode in which a CPU can access the data stored in them. NOR Flash is designed to replace the EPROM in applications that executes code directly from the memory device. NOR has random access type architecture and minimizes access time for random reads-through memory. For this reason, it is typically used for code storage. Another functionality offered in NOR Flash, unavailable so far in NAND, is the ability to perform execute-in-place (XIP). XIP is the execution of an application directly from the Flash instead of having to download the code into the system's RAM before executing it.
NAND Flash is designed mainly for mass storage and implements a sequential access type architecture, which minimizes the cell size and the cost. For this reason, it is typically used for data storage where high capacities (i.e. more then 4 Mbytes) are needed.
NAND technology has always been considered as superior data storage medium where Flash storage is a necessity. Targeting the emulation of disk drives, it breaks down the medium into pages, typically 256 bytes or 512 bytes per page. Those pages are just like the hard drive's sectors and thus provide a known environment to the system. The data is stored and retrieved from the Flash by transferring a full page during every access.
The erase transaction with NAND is faster than with NOR because the erase block size is only 8 Kbytes compared with 64 Kbytes. For example, with NOR, even when only 1 byte needs to be updated, a whole section of 64 Kbytes must be erased and then rewritten. Clearly, it takes less time to erase and update 8 Kbytes than 64 Kbytes.
Two other major benefits of the NAND architecture are size and cost effectiveness. NAND footprint size remains the same as densities increase, whereas the NOR footprint increases with density. NAND is about 40% less expensive than NOR.
Sequence
The traditional approach for initializing the system consists of a boot device, CPU, DRAM and a disk. When power is supplied to the system and a reset signal is generated, the components change from an unknown state to a known state but are not accessible yet. Once the reset signal is negated, all components are still in the same pre-determined state but can be accessed. The address that the CPU places on the bus at this stage points to a location in memory that contains the reset vector. In order to ensure compatibility, this address is typically both at the top (e.g. 0xFFFFFFF0) or bottom (e.g. 0x00000000) of the CPU's address space. Only after it accessed this address can the CPU starts to fetch instructions, data, or a jump address from the reset vector location. The reset vector is stored in a non-volatile device, typically a ROM, EPROM or flash that supports direct code execution or XIP. These instructions usually initialize the hardware functions (e.g. chipset registers), copy the operating system and drivers from the disk into RAM, and then, start the operating system. Once the operating system is loaded into the system's RAM, it takes the control over the system.
M-Systems' DiskOnChip products are based on NAND Flash (Fig 1). It includes the company's proprietary True Flash File System (TrueFFS) technology, providing complete read and write capabilities and hard disk emulation at both sector and file levels. The TrueFFS also takes care of power failures and provides data reliability, error detection and correction (EDC/ECC), bad block management and wear leveling. With the DiskOnChip Millennium Plus the sustained write speed is over 1.5 Mbytes/s, sustained read speed is over 3 Mbytes/s and the burst read/write transfer is of 20 Mbytes/s.
Combining Storage, Boot Functions
Using the boot replacement technique, the DiskOnChip products can be the boot device for both the basic hardware initialization code and the operating system. This can eliminate the need for a separate boot flash chip, which saves both costs and handling efforts. The CPU can fetch and execute the boot code directly from the XIP boot-block of the DiskOnChip. It then loads the remainder of the boot code from the NAND flash memory into the system's RAM and continues the standard boot process.
The traditional boot sequence, as previously described, is modified when using one of the DiskOnChip products or the DiskOnChip2000 TSOP. The modified process includes two additional phases contained in two code modules. The first code module, known as the Initial Program Loader (IPL), is responsible for initializing the minimum hardware setup, loading the next piece of code from the DiskOnChip into the system's RAM and executing it. The second code module loads the rest of the initialization code, known as the Secondary Program Loader (SPL), from the DiskOnChip into the system's RAM.
When the CPU board wakes up after reset, the IPL code is automatically transferred from the first block of flash (Step 1,Fig 2) into the XIP boot-block of the DiskOnChip. This operation is required because the XIP boot-block is actually a small area (512 bytes or 1 Kbytes) of SRAM (volatile memory). Now when the CPU fetches the reset vector, it points to the XIP boot-block of the DiskOnChip, where the IPL resides (Step 2, Fig 2). The IPL consists of a stripped down routine that operates the checksum test only on a small portion of the system's RAM, just enough to contain the SPL code. The IPL copies the SPL to the system's RAM and then the SPL code is executed (Steps 3 and 4, Fig 2). From this stage on, the boot process is the same as the traditional one. The rest of the system's RAM is scanned, all the hardware functions are initialized, the operating system is copied to the system's RAM (Step 5, Fig 2) and takes control (Step 6, Fig 2).
While so far systems had one flash chip storing BIOS and another storing data, M-Systems has come up with a single chip that does it all. With the DiskOnChip2000 TSOP and DiskOnChip Millennium products, designers need to use only one device for boot and storage purposes. These unique solutions lower design and operational costs while shortening time-to-market and providing a competitive advantage.
by Sharon Tikotzky, Director of Marketing, M-Systems, Inc, USA
(July 2002 Issue, Nikkei Electronics Asia)
What is Flash Memory?
Flash memory is a type of constantly powered non-volatile memory that can be erased and reprogrammed in units of memory called blocks. It got its name because the microchip is organized so that a section of memory cells is erased in a single action, or Flash. Flash is actually a variation of the EEPROM with much faster updating speed.
The most common Flash types are NOR and NAND and they can be differentiated from each other by the mode in which a CPU can access the data stored in them. NOR Flash is designed to replace the EPROM in applications that executes code directly from the memory device. NOR has random access type architecture and minimizes access time for random reads-through memory. For this reason, it is typically used for code storage. Another functionality offered in NOR Flash, unavailable so far in NAND, is the ability to perform execute-in-place (XIP). XIP is the execution of an application directly from the Flash instead of having to download the code into the system's RAM before executing it.
NAND Flash is designed mainly for mass storage and implements a sequential access type architecture, which minimizes the cell size and the cost. For this reason, it is typically used for data storage where high capacities (i.e. more then 4 Mbytes) are needed.
NAND technology has always been considered as superior data storage medium where Flash storage is a necessity. Targeting the emulation of disk drives, it breaks down the medium into pages, typically 256 bytes or 512 bytes per page. Those pages are just like the hard drive's sectors and thus provide a known environment to the system. The data is stored and retrieved from the Flash by transferring a full page during every access.
The erase transaction with NAND is faster than with NOR because the erase block size is only 8 Kbytes compared with 64 Kbytes. For example, with NOR, even when only 1 byte needs to be updated, a whole section of 64 Kbytes must be erased and then rewritten. Clearly, it takes less time to erase and update 8 Kbytes than 64 Kbytes.
Two other major benefits of the NAND architecture are size and cost effectiveness. NAND footprint size remains the same as densities increase, whereas the NOR footprint increases with density. NAND is about 40% less expensive than NOR.
Sequence
The traditional approach for initializing the system consists of a boot device, CPU, DRAM and a disk. When power is supplied to the system and a reset signal is generated, the components change from an unknown state to a known state but are not accessible yet. Once the reset signal is negated, all components are still in the same pre-determined state but can be accessed. The address that the CPU places on the bus at this stage points to a location in memory that contains the reset vector. In order to ensure compatibility, this address is typically both at the top (e.g. 0xFFFFFFF0) or bottom (e.g. 0x00000000) of the CPU's address space. Only after it accessed this address can the CPU starts to fetch instructions, data, or a jump address from the reset vector location. The reset vector is stored in a non-volatile device, typically a ROM, EPROM or flash that supports direct code execution or XIP. These instructions usually initialize the hardware functions (e.g. chipset registers), copy the operating system and drivers from the disk into RAM, and then, start the operating system. Once the operating system is loaded into the system's RAM, it takes the control over the system.
M-Systems' DiskOnChip products are based on NAND Flash (Fig 1). It includes the company's proprietary True Flash File System (TrueFFS) technology, providing complete read and write capabilities and hard disk emulation at both sector and file levels. The TrueFFS also takes care of power failures and provides data reliability, error detection and correction (EDC/ECC), bad block management and wear leveling. With the DiskOnChip Millennium Plus the sustained write speed is over 1.5 Mbytes/s, sustained read speed is over 3 Mbytes/s and the burst read/write transfer is of 20 Mbytes/s.
Combining Storage, Boot Functions
Using the boot replacement technique, the DiskOnChip products can be the boot device for both the basic hardware initialization code and the operating system. This can eliminate the need for a separate boot flash chip, which saves both costs and handling efforts. The CPU can fetch and execute the boot code directly from the XIP boot-block of the DiskOnChip. It then loads the remainder of the boot code from the NAND flash memory into the system's RAM and continues the standard boot process.
The traditional boot sequence, as previously described, is modified when using one of the DiskOnChip products or the DiskOnChip2000 TSOP. The modified process includes two additional phases contained in two code modules. The first code module, known as the Initial Program Loader (IPL), is responsible for initializing the minimum hardware setup, loading the next piece of code from the DiskOnChip into the system's RAM and executing it. The second code module loads the rest of the initialization code, known as the Secondary Program Loader (SPL), from the DiskOnChip into the system's RAM.
When the CPU board wakes up after reset, the IPL code is automatically transferred from the first block of flash (Step 1,Fig 2) into the XIP boot-block of the DiskOnChip. This operation is required because the XIP boot-block is actually a small area (512 bytes or 1 Kbytes) of SRAM (volatile memory). Now when the CPU fetches the reset vector, it points to the XIP boot-block of the DiskOnChip, where the IPL resides (Step 2, Fig 2). The IPL consists of a stripped down routine that operates the checksum test only on a small portion of the system's RAM, just enough to contain the SPL code. The IPL copies the SPL to the system's RAM and then the SPL code is executed (Steps 3 and 4, Fig 2). From this stage on, the boot process is the same as the traditional one. The rest of the system's RAM is scanned, all the hardware functions are initialized, the operating system is copied to the system's RAM (Step 5, Fig 2) and takes control (Step 6, Fig 2).
While so far systems had one flash chip storing BIOS and another storing data, M-Systems has come up with a single chip that does it all. With the DiskOnChip2000 TSOP and DiskOnChip Millennium products, designers need to use only one device for boot and storage purposes. These unique solutions lower design and operational costs while shortening time-to-market and providing a competitive advantage.
by Sharon Tikotzky, Director of Marketing, M-Systems, Inc, USA
(July 2002 Issue, Nikkei Electronics Asia)
