![[Tech-On!]Tech News-Straight from Asia](/english/img/06/logo1.gif){kind=logo}
[Trade Shows] SEMICON China Scrutinizes Manufacturing Issues
| Geographic Eligibility (Edition) | Medium (Click where applicable) |
|---|---|
| Hong Kong, Malaysia, the Philippines, Singapore and Thailand (English) | Magazine + e-newsletter E-newsletter only |
| India (English) | Digital magazine + e-newsletter E-newsletter only |
| Taiwan (Complex Chinese) |
Magazine + e-newsletter E-newsletter only |
| South Korea(Korean) | Magazine + e-newsletter E-newsletter only |
| Other countries/regions | E-newsletter only *Readers from other countries/regions who want to receive Nikkei Electronics Asia printed magazine may consider paid subscription. Please contact NE Asia Circulation Department for details. |
SEMICON China 2002 marked another step in the IC industry's inexorable march into China. Official auguries expect to see more than thirty 8- and 12-inch wafer fabs in Shanghai alone in another 10-12 years. Of the six fabs now operating in the province, Grace Semiconductor, Advanced Semiconductor, and Shanghai Bell are in various stages of project transfer, while Applied Materials, Photronics, and KLA-Tencor are in the process of setting up shop. US-based Photronics will build a plant, to be operational next year in Shanghai's Zhangjiang Hi-Tech Industrial Zone, to develop reticles for 0.13 micron processes and 12-inch fabs.
Three Japanese companies - FerroTec Corp, Toshiba Ceramic Co Ltd, and Mitsui & Co Ltd - will invest US$24 million this year in building a monocrystal silicon wafer production line in Shanghai. The plant will have the capacity to turn out 50,000 6-inch wafers a month.
High-Speed Growth
At the Technical Symposium held concurrently with the show, Gerald Li, president of KLA-Tencor China, highlighted new technologies in yield management which can handle the complexity arising out of the convergence of copper and low-k material interconnects, sub-wavelength lithography, and 300mm wafers. Li said controlling lithography must be at the center of any yield management strategy, since it continues to be the most complex and expensive of all processes to maintain within the fab, amounting to as much as 35% of the overall chip manufacturing costs.
According to the International Technology Roadmap for Semiconductors (ITRS 2001), overlay tolerance for 90-nanomater IC production will be 31nm, a drop of 14nm from the tolerance level needed at 130-nanometer IC production. Li calculates that a variation of even a single nanometer outside a process window in a 130nm lithography process, in a state-of-the-art fab, can cost the fab up to US$12 million a year.
Current industry practices for measuring process windows rely on onboard metrology capabilities of lithography tools to determine the best focus and exposure settings, but they do not determine the size of the process windows. They require the lithography tool to remain offline while measurements are taken, which can cut into the tool's productivity. It is possible to get the lithography tools to pattern more wafers by offloading critical CD (critical dimension) process window measurements from the tools onto optical CD and CD SEM metrology systems. This also makes for greater measurement accuracy. Li cited 3x improvements in focus and exposure dose matching across three critical layers in a set-up utilizing CD SEM metrology systems with automated CD process window monitoring capabilities.
Li called attention to backside contaminants, which account for 0.4% to 10% of a fab's chronic annual yield loss, and the impact of which will only rise further with the migration to 300mm format. Until recently, backside defects were detected through visual inspection after manually flipping wafers with a vacuum wand. Subjecting the patterned side of wafers to a vacuum could damage them, and defects were often missed. New automated edge-only wafer contact methods now ensure cleanness of the unscanned side while enabling monitoring of the wafer backside.
US-based Siliconware, Inc underlined the advantages of packaging for mobile communication devices. The ability to vertically stack dies within a standard package form factor which addresses their short technology and market lifecycles. Stacking SRAM and Flash in a chip scale package (CSP) plus an ASIC allows off-the-shelf assembly of products and avoids very expensive integration-on-wafer solutions. Siliconware is in production with stacked thin and fine-pitch ball grid array (STFBGA) products, and is prototyping multichip BGA (MCBGA) with which multiple CSPs are attached to the BGA package.
Critical pointers to the inadequacy of trained human resources within the country moderate the euphoria attending the growth of the semiconductor industry in China. "If Chinese firms do not have the independent intellectual property right, the long-term interests of the country's information industry will be jeopardized," said Jia Li and Han Meng, researchers at the Institute of Economics under the Chinese Academy of Social Sciences.
by M K Shankar
(June 2002 Issue, Nikkei Electronics Asia)
Three Japanese companies - FerroTec Corp, Toshiba Ceramic Co Ltd, and Mitsui & Co Ltd - will invest US$24 million this year in building a monocrystal silicon wafer production line in Shanghai. The plant will have the capacity to turn out 50,000 6-inch wafers a month.
High-Speed Growth
At the Technical Symposium held concurrently with the show, Gerald Li, president of KLA-Tencor China, highlighted new technologies in yield management which can handle the complexity arising out of the convergence of copper and low-k material interconnects, sub-wavelength lithography, and 300mm wafers. Li said controlling lithography must be at the center of any yield management strategy, since it continues to be the most complex and expensive of all processes to maintain within the fab, amounting to as much as 35% of the overall chip manufacturing costs.
According to the International Technology Roadmap for Semiconductors (ITRS 2001), overlay tolerance for 90-nanomater IC production will be 31nm, a drop of 14nm from the tolerance level needed at 130-nanometer IC production. Li calculates that a variation of even a single nanometer outside a process window in a 130nm lithography process, in a state-of-the-art fab, can cost the fab up to US$12 million a year.
Current industry practices for measuring process windows rely on onboard metrology capabilities of lithography tools to determine the best focus and exposure settings, but they do not determine the size of the process windows. They require the lithography tool to remain offline while measurements are taken, which can cut into the tool's productivity. It is possible to get the lithography tools to pattern more wafers by offloading critical CD (critical dimension) process window measurements from the tools onto optical CD and CD SEM metrology systems. This also makes for greater measurement accuracy. Li cited 3x improvements in focus and exposure dose matching across three critical layers in a set-up utilizing CD SEM metrology systems with automated CD process window monitoring capabilities.
Li called attention to backside contaminants, which account for 0.4% to 10% of a fab's chronic annual yield loss, and the impact of which will only rise further with the migration to 300mm format. Until recently, backside defects were detected through visual inspection after manually flipping wafers with a vacuum wand. Subjecting the patterned side of wafers to a vacuum could damage them, and defects were often missed. New automated edge-only wafer contact methods now ensure cleanness of the unscanned side while enabling monitoring of the wafer backside.
US-based Siliconware, Inc underlined the advantages of packaging for mobile communication devices. The ability to vertically stack dies within a standard package form factor which addresses their short technology and market lifecycles. Stacking SRAM and Flash in a chip scale package (CSP) plus an ASIC allows off-the-shelf assembly of products and avoids very expensive integration-on-wafer solutions. Siliconware is in production with stacked thin and fine-pitch ball grid array (STFBGA) products, and is prototyping multichip BGA (MCBGA) with which multiple CSPs are attached to the BGA package.
Critical pointers to the inadequacy of trained human resources within the country moderate the euphoria attending the growth of the semiconductor industry in China. "If Chinese firms do not have the independent intellectual property right, the long-term interests of the country's information industry will be jeopardized," said Jia Li and Han Meng, researchers at the Institute of Economics under the Chinese Academy of Social Sciences.
by M K Shankar
(June 2002 Issue, Nikkei Electronics Asia)
