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APack Develops MCP Processes
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APack Technologies Inc of Taiwan specializes in wafer solder bump and flip chip technologies. Using technology originally licensed from Lucent Technologies Inc in 1996, APack engineers have received training and technology transference from Lucent in I/O redistribution, wafer bumping and flip-chip-on-silicon or organic substrates. Since then, APack has developed its own technology multi-chip packaging (MCP) processes.
Putting solder I/O bumps onto ICs while they still are on the wafer is the basic technology transferred from Lucent. The solder bumps provide lower resistance and thus allow for higher transmission efficiency and speed with lower inductance than with traditional wire bonding. "We provide I/O rerouting design services for our customers as well as fabricating the different layers necessary for solder wafer bumping," said Kuo-Lian Won, vice president of marketing and sales for APack. The rerouting service helps keep design costs down since it moves I/O pads from the peripheral footprint to an area array without having to redesign the die.
The basic solder wafer bump has an aluminum I/O pad embedded into the silicon wafer. There is then a dielectric layer above it. A rerouting metal carries the electrical signal from the I/O pad to a UBM (under bumping metal) on which the solder bump sits. "The exact composition of the UBM is a proprietary secret," said Won. "It's basically a chrome or copper alloy."
CMOS, BiCMOS and bipolar device types are supported for bumping on either 6- or 8-inch wafers. The maximum chip size currently supported is 8mm x 8mm, with the potential for over a thousand I/O points. The solder ball pitch can be from 0.8mm to 0.5mm and the ball is usually a 63/37 tin/lead alloy.
APack has advanced the basic wafer level solder bump by adding a passivation layer and then a protective plastic layer over the dielectric. A solder column carries the electric signal from the UBM to the solder ball. Using this kind of packaging, an individual IC can be mounted directly onto a PCB using standard SMT (surface mount technology) equipment. The reliability of wafer bump packaging is a major concern. APack claims that it is the only facility that can offer such packaging able to withstand 1800 heating/cooling reliability test cycles. "In such a test, we heat the package to 125 degrees centigrade and then cool it to minus 20 degrees centigrade for each cycle," said Won.
Mounted Chips
Flip chip packaging carries wafer solder bump technology a step further by mounting chips on top of chips. SRAM to Flash is the standard flip chip package. "The customer provides us with the mother wafer and the daughter wafers," said Won. "We then make a mask of the interconnect between the two chips."
The daughter ICs are cut from their wafer. The solder bumps are fabricated onto the mother wafer and the daughter chips are then mounted onto the mother wafer. Typically about 60 solder bumps are used between the two chips. Advantages to flip chip technology are one-operation bonding, improved electrical performance, smaller die size with a lower profile and direct thermal dissipation.
APack is currently ramping up MCP and chip scale packaging (CSP) for the production of minimodules. After the flip chip on chip is cut, they are mounted onto a substrate, usually with one of the chips embedded into the substrate. The substrate can then be solder bump mounted onto a PCB. Typically, about a 400-lead BGA type package is used at this final step.
"The solder bumps that mount the minimodule to the PCB are usually larger than those for the flip chip or wafer bumping," said Won. "We need to work out with the customer what size to use, and that depends on what kind of substrate is used. If the heat expansion coefficient is different than that of the PCB then there can be peeling."
Possible combinations of different functional chips that can be flip chip packaged and then put into an MCP include a DSP with two SRAMs, an FPGA with Flash, a graphics controller with SDRAM and stacked DRAM.
Smaller and faster is a trend in electronic products that goes beyond cell phones. "We see a demand for our packaging process technology for Bluetooth products for example," said Won. "Other products which benefit from this technology include IC cards, notebooks, PDAs, digital cameras and wireless LAN equipment."
by David Baldwin
Websites:
APack Technologies: http://www.apack.com.tw
ASE: http://www.asetwn.com.tw
Lucent Technologies: http://www.lucent.com
(April 2002 Issue, Nikkei Electronics Asia)
Putting solder I/O bumps onto ICs while they still are on the wafer is the basic technology transferred from Lucent. The solder bumps provide lower resistance and thus allow for higher transmission efficiency and speed with lower inductance than with traditional wire bonding. "We provide I/O rerouting design services for our customers as well as fabricating the different layers necessary for solder wafer bumping," said Kuo-Lian Won, vice president of marketing and sales for APack. The rerouting service helps keep design costs down since it moves I/O pads from the peripheral footprint to an area array without having to redesign the die.
The basic solder wafer bump has an aluminum I/O pad embedded into the silicon wafer. There is then a dielectric layer above it. A rerouting metal carries the electrical signal from the I/O pad to a UBM (under bumping metal) on which the solder bump sits. "The exact composition of the UBM is a proprietary secret," said Won. "It's basically a chrome or copper alloy."
CMOS, BiCMOS and bipolar device types are supported for bumping on either 6- or 8-inch wafers. The maximum chip size currently supported is 8mm x 8mm, with the potential for over a thousand I/O points. The solder ball pitch can be from 0.8mm to 0.5mm and the ball is usually a 63/37 tin/lead alloy.
APack has advanced the basic wafer level solder bump by adding a passivation layer and then a protective plastic layer over the dielectric. A solder column carries the electric signal from the UBM to the solder ball. Using this kind of packaging, an individual IC can be mounted directly onto a PCB using standard SMT (surface mount technology) equipment. The reliability of wafer bump packaging is a major concern. APack claims that it is the only facility that can offer such packaging able to withstand 1800 heating/cooling reliability test cycles. "In such a test, we heat the package to 125 degrees centigrade and then cool it to minus 20 degrees centigrade for each cycle," said Won.
Mounted Chips
Flip chip packaging carries wafer solder bump technology a step further by mounting chips on top of chips. SRAM to Flash is the standard flip chip package. "The customer provides us with the mother wafer and the daughter wafers," said Won. "We then make a mask of the interconnect between the two chips."
The daughter ICs are cut from their wafer. The solder bumps are fabricated onto the mother wafer and the daughter chips are then mounted onto the mother wafer. Typically about 60 solder bumps are used between the two chips. Advantages to flip chip technology are one-operation bonding, improved electrical performance, smaller die size with a lower profile and direct thermal dissipation.
APack is currently ramping up MCP and chip scale packaging (CSP) for the production of minimodules. After the flip chip on chip is cut, they are mounted onto a substrate, usually with one of the chips embedded into the substrate. The substrate can then be solder bump mounted onto a PCB. Typically, about a 400-lead BGA type package is used at this final step.
"The solder bumps that mount the minimodule to the PCB are usually larger than those for the flip chip or wafer bumping," said Won. "We need to work out with the customer what size to use, and that depends on what kind of substrate is used. If the heat expansion coefficient is different than that of the PCB then there can be peeling."
Possible combinations of different functional chips that can be flip chip packaged and then put into an MCP include a DSP with two SRAMs, an FPGA with Flash, a graphics controller with SDRAM and stacked DRAM.
Smaller and faster is a trend in electronic products that goes beyond cell phones. "We see a demand for our packaging process technology for Bluetooth products for example," said Won. "Other products which benefit from this technology include IC cards, notebooks, PDAs, digital cameras and wireless LAN equipment."
by David Baldwin
Websites:
APack Technologies: http://www.apack.com.tw
ASE: http://www.asetwn.com.tw
Lucent Technologies: http://www.lucent.com
(April 2002 Issue, Nikkei Electronics Asia)
