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PLD Methodology Lifts Performance by 40%
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Altera Corp has developed a new programmable logic device (PLD) design methodology, the Stratix methodology, to boost the performance of broadband designs. Compared with the current leading-edge 0.13micron PLD, the APEX II, the Stratix methodology boosts performance in the "Push-Button" benchmark (a kind of a default benchmark) by 40%, and enables a 20% reduction in silicon real estate.
The Stratix methodology consists of three key architectures: LogicLock optimized block core design; MultiTrack, with three interconnect lengths; and DirectDrive uniform routing.
With the LogicLock architecture, the user does not need to consider optimization of block-to-block performance, and can focus on a target block inside. If a block must have a performance of 100MHz, the user needs only take into consideration 100MHz performance design, without the need for compromise, as with designing a locked block.
MultiTrack design architecture has three kinds of interconnect lengths: one short and narrow with a buffer designed for internal block; one of medium length and width with a slightly larger current drivability designed for block-to-block interconnect; and one long and wide with the largest drivability designed for busing. These lines deliver eight times higher performance, reduce the area by 50%, and offer routing four times more effective.
DirectDrive technology provides consistent access of logic blocks to routing. Each block has interface lines to obtain uniform access to other blocks. This architecture limits routing congestion and enables block locking.
(April 2002 Issue, Nikkei Electronics Asia)
The Stratix methodology consists of three key architectures: LogicLock optimized block core design; MultiTrack, with three interconnect lengths; and DirectDrive uniform routing.
With the LogicLock architecture, the user does not need to consider optimization of block-to-block performance, and can focus on a target block inside. If a block must have a performance of 100MHz, the user needs only take into consideration 100MHz performance design, without the need for compromise, as with designing a locked block.
MultiTrack design architecture has three kinds of interconnect lengths: one short and narrow with a buffer designed for internal block; one of medium length and width with a slightly larger current drivability designed for block-to-block interconnect; and one long and wide with the largest drivability designed for busing. These lines deliver eight times higher performance, reduce the area by 50%, and offer routing four times more effective.
DirectDrive technology provides consistent access of logic blocks to routing. Each block has interface lines to obtain uniform access to other blocks. This architecture limits routing congestion and enables block locking.
(April 2002 Issue, Nikkei Electronics Asia)
