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SiGe Technology Breaks 200GHz Barrier
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The cut-off frequency fT of SiGe-based bipolar transistors has doubled to surpass 200GHz (Fig 1). This SiGe technology has applications in optical communications integrated circuits (IC) with transfer rates of 40 Gbits/s.
Previously announced SiGe chips are already entering use in short-haul links, but the SiGe technology, with doubled performance, will be able to handle the demands of longhaul communication ICs as well. Why employ SiGe technology in optical communications first? Tad Yamaguchi, technology development executive director, Maxim Integrated Products, Inc of the US, said, "The systems side wanted a cheap, SiGe technology-based IC for optical communications systems hitting 40 Gbits/s."
ICs using SiGe technology are expected to take off not only in optical communications, but also in cellular telephones, wireless local area networks (LAN) and other wireless communication applications. The major reason for this is that SiGe technology, with its improved performance, is also likely to be able to slash dissipation to half what it is now. In cell phones, the new technology is likely to accelerate the appearance of the single-chip cell phone, using SiGe and complementary metal-oxide semiconductor (CMOS) technologies to build all the cell phone functions into a single chip.
IBM Roll Out
IBM Corp was responsible for a sudden doubling in the performance of SiGe technology by developing a SiGe transistor in May 2001 with fT of 210GHz.1 The firm went on to develop a SiGe heterojunction bipolar transistor (HBT) with an fT of 210GHz, and fMAX of 200GHz, announcing it at the International Solid-State Circuits Conference 2002 (ISSCC 2002).
At the 2001 International Electron Devices Meeting (IEDM) held in December 2001, Conexant Systems Inc of the US also announced a device with a cut-off frequency of 200GHz.2 Other semiconductor manufacturers and research institutes have been boosting SiGe technology performance since 2000, raising the overall technology level (Fig 2).
More manufacturers are entering the field. While the area was originally monopolized by IBM, today about a dozen other manufacturers have joined. Taiwan Semiconductor Manufacturing Co, Ltd (TSMC), the world's largest foundry, has also begun its own process.
Surpassing Limits
One might well ask why SiGe technology has evolved so fast and gone so far. Until recently, most engineers in the field accepted that 100GHz was the practical limit. Once the fT (a frequency at a current amplification ratio beta of 1) for a Si-based material reaches 200GHz, the voltage margin is reduced and the signal/noise (S/N) ratio deteriorates, because the collector-emitter breakdown voltage (BVCEO) is only 1V.3 This assumption was based on the fact that the product of fT and BVCEO is material-dependent, and Si-based devices such as SiGe HBT or CMOS transistors were about 200GHzV.
The limit of 200GHzV was proposed back in 1965, however; quite some time ago. This value was based on peak electron velocity and electric field which causes Si breakdown, but both values have changed considerably since then. In fact, some in the industry have expressed doubt as to the validity of the 200GHzV value in recent years.
Now, BVCEO has been raised to about 2V, "just barely within the level of possible commercialization," according to Maxim's Yamaguchi, and fT has been boosted. While the resulting device offers an absolute performance still inferior to InP technology, it is practical. "Calculation of the theoretical performance based on physical properties yields over 1 THzV," claims Katsuyoshi Washio, senior research scientist, ULSI Research Department, Central Research Laboratory, Hitachi Ltd. Many engineers agree with him, claiming that there is still considerable room for future improvement --not only SiGe engineers, but InP engineers as well.
Improvements in SiGe film growth process technology brought values closer to the theoretical limit. Technological competition among semiconductor manufacturers has driven the improvement of SiGe technology designed for 10-Gbit/s optical communication ICs and RF front-end ICs for cell phones and wireless LAN applications. One result of the competition is that the technology for forming low-defect films has almost been established, according to Teruhito Ohnishi, senior staff researcher, Advanced Technology Research Laboratories, Matsushita Electric Industrial Co, Ltd.
Boosting fMAX
If only fT is increased, then the benefits are only available to ICs processing digital signals, such as multiplexers and demultiplexers. If the maximum oscillation frequency (fMAX) can also be increased, it would provide a performance improvement for analog ICs, such as pre-amps, bandwidth-limited amps and voltage-controlled oscillators (VCO). Engineers want to increase integration levels in the chips, and so semiconductor engineers are working to solve two problems: increasing fMAX and increasing CMOS transistor integration density without sacrificing SiGe HBT performance.
A look at the performance of the devices announced at 2001 IEDM indicates that both fT and fMAX values are on the way up (Fig 3). Semiconductor manufacturers are looking to new transistor structures (Fig 4) minimizing parasitic resistance and capacitance, which makes it harder to boost fMAX. Instead of relying solely on lithography, they have adopted self-alignment technology with which finer line structures can be readily available.
An increase in fT for SiGe HBT can be accomplished by reducing the thickness of the base layer in the bipolar structure. If the thickness of the extrinsic base linking the base to the base electrode is also reduced, then resistance between base and base electrode (called the base resistance) rises. The value of fMAX will rise with fT, but because base resistance also increases, a cap is imposed on fMAX improvement.
The base resistance can be easily dropped by making the extrinsic base thick. Conexant reduced base resistance by embedding p+ layer into the extrinsic base, achieving the best to date SiGe HBT with an fT of 200GHz and an fMAX of 180GHz. The firm claims that further thinning of dimensions will boost both values over 200GHz.
Parasitic Capacitance
Hitachi's process is to form a thicker extrinsic base before the base layer formation. Their approach is effective in reducing parasitic capacitance, and while the Hitachi prototype SiGe HBT slashes both parasitic resistance and parasitic capacitance to achieve an fT of 124GHz (lower than Conexant's achievement), fMAX is relatively high at 174GHz.4 Parasitic capacitance is lowered because the emitter and collector regions are about the same size, decreasing the overlap region.
Technologies for integrating an analog SiGe HBT front-end circuit with baseband circuit, digital signal processors (DSP) and other digital CMOS circuits also demonstrated progress at 2001 IEDM. One especially eye-catching presentation was Hitachi's SiGeC technology, which adds carbon to SiGe. Carbon acts to relieve distortion in the SiGe, boosting the breakdown voltage.
When SiGe HBT and CMOS transistors are integrated, the SiGe HBT is first formed, and then heat treatment is used to activate the n- and p-type dopants in CMOS transistor sources and drains. Temperatures reach 1,000Centigrade, which can degrade SiGe HBT characteristics.
When carbon is added to the base SiGe layer it restrains the dispersion of boron (base dopant) into the bipolar transistor emitter and collector, maintaining a high boron concentration in the base, and providing an increase of about 25% in fT and fMAX.
Finer-Line MOS
The performance of MOS technology is also improving. Fujitsu Laboratories Ltd announced an nMOS transistor with an fMAX of 185GHz -- double the previous high -- at IEDM 2001.5 While the fT of 120GHz is still inferior to that of SiGe HBT (200GHz), fMAX is better by 5GHz.
According to the International Technology Roadmap for Semiconductors (ITRS), which defines future performance demands for CMOS technology, practical MOS transistors with an fMAX of 185GHz are not expected until 2016. According to Toshihiro Sugii, director, Advanced Device Department, C Project Group, Fujitsu Laboratories, "We can use the process technology of logic ICs, and we will be able to make Bi-CMOS ICs with the same process count."
If MOS transistors achieve an fT of 200GHz, on a par with existing SiGe HBT, it would mean a gate length of about 50nm, equivalent to cutting-edge technology slated for implementation in microprocessors in 2005. Within three years, it would be a proven volume-production technology. However, MOS transistors would suffer from variation in electrical characteristics, which grows more severe as geometry shrinks, and as a result, some in the industry feel that advanced logic IC processes will not be applicable to analog signal processing ICs.
Reducing Rgate, Cparas
CMOS technology has always increased transistor operating speed by reducing geometry, and fT has steadily risen apace.
The situation is different for fMAX, though. Shrinking dimensions mean shorter gate lengths and therefore faster transistor switching, but at the same time gate resistance rises, making it harder to boost fMAX. The situation is the same with SiGe HBT, where thinning the base to boost fT results in higher base resistance and imposes a ceiling on fMAX.
Fujitsu Laboratories has three methods to increase fMAX in its MOS transistors, namely: (1) reducing gate resistance by adding metal on top of the gate electrode; (2) using dynamic-threshold MOS (DTMOS) to shorten the gate and the substrate, boosting fT ; and, (3) using totally-depleted silicon-on-insulator (SOI) wafers to minimize parasitic capacitance.
Of these, the metal deposition on the gate electrode was the most effective. An Al coating slashed gate resistance by 1/200th. Compared to a design without the Al metallization, fMAX is about three times higher.
Mixed Signal Circuits
At 2001 IEDM, Mitsubishi Electric Corp used a different approach to improve fMAX, achieving a respectable 135GHz6, although it was less than what has been achieved by Fujitsu Laboratories. The firm focused on slashing parasitic capacitance between gate and drain, and between gate and source (Fig 5). Mitsubishi's approach is to single-chip logic and analog signal processing, optimizing overlapped regions of a source and drain under the gate dielectric layer to match each circuit.
For example, source and drain areas are made larger for logic circuits, which are less susceptible to parasitic capacitance, reducing the distance between the source and drain to boost operating speed. The opposite approach is used in circuits with analog signal processing.
by Satoshi Okubo
Websites:
Conexant Systems: http://www.conexant.com
Fujitsu Laboratories: http://www.labs.fujitsu.com/en
Hitachi: http://global.hitachi.com
IBM: http://www.ibm.com
Matsushita Electric Industrial: http://www.panasonic.co.jp/global
Mitsubishi Electric: http://www.mitsubishielectric.com
References:
1) Jeng, S. J, et al, "A 210-GHz fT SiGe HBT With a Non-Self-Aligned Structure," IEEE Electron Device Letters, pp 542-544, Nov 2001.
2) Racanelli, M, et al, "Ultra High Speed SiGe NPN for Advanced BiCMOS Technology," 2001 International Electron Devices Meeting Technical Digest, pp 336-339, Dec 2001.
3) Kato, M, Yomogita, H and Ookubo, S, "Bluetooth Expedites Moves for CMOS RF Chip," pp 46-51, vol 10, no 6, Nikkei Electronics Asia, June 2001.
4) Oda, K, et al, "Self-Aligned Selective-Epitaxial-Growth Si1-x-y GexCy HBT Technology Featuring 170-GHz fMAX ," 2001 International Electron Devices Meeting Technical Digest, pp 332-335, Dec 2001.
5) Hirose, T, et al, "A 185-GHz fMAX SOI DTMOS with A New Metallic Overlaygate for Low-power RF Applications," ibid, pp 943-945, Dec 2001.
6) Matsumoto, T, et al, "70nm SOI-CMOS of 135-GHz fMAX with Dual OffsetImplanted Source-Drain Extension Structure for RF/Analog and Logic Applications," ibid, pp 219-222, Dec 2001.
(April 2002 Issue, Nikkei Electronics Asia)
Previously announced SiGe chips are already entering use in short-haul links, but the SiGe technology, with doubled performance, will be able to handle the demands of longhaul communication ICs as well. Why employ SiGe technology in optical communications first? Tad Yamaguchi, technology development executive director, Maxim Integrated Products, Inc of the US, said, "The systems side wanted a cheap, SiGe technology-based IC for optical communications systems hitting 40 Gbits/s."
ICs using SiGe technology are expected to take off not only in optical communications, but also in cellular telephones, wireless local area networks (LAN) and other wireless communication applications. The major reason for this is that SiGe technology, with its improved performance, is also likely to be able to slash dissipation to half what it is now. In cell phones, the new technology is likely to accelerate the appearance of the single-chip cell phone, using SiGe and complementary metal-oxide semiconductor (CMOS) technologies to build all the cell phone functions into a single chip.
IBM Roll Out
IBM Corp was responsible for a sudden doubling in the performance of SiGe technology by developing a SiGe transistor in May 2001 with fT of 210GHz.1 The firm went on to develop a SiGe heterojunction bipolar transistor (HBT) with an fT of 210GHz, and fMAX of 200GHz, announcing it at the International Solid-State Circuits Conference 2002 (ISSCC 2002).
At the 2001 International Electron Devices Meeting (IEDM) held in December 2001, Conexant Systems Inc of the US also announced a device with a cut-off frequency of 200GHz.2 Other semiconductor manufacturers and research institutes have been boosting SiGe technology performance since 2000, raising the overall technology level (Fig 2).
More manufacturers are entering the field. While the area was originally monopolized by IBM, today about a dozen other manufacturers have joined. Taiwan Semiconductor Manufacturing Co, Ltd (TSMC), the world's largest foundry, has also begun its own process.
Surpassing Limits
One might well ask why SiGe technology has evolved so fast and gone so far. Until recently, most engineers in the field accepted that 100GHz was the practical limit. Once the fT (a frequency at a current amplification ratio beta of 1) for a Si-based material reaches 200GHz, the voltage margin is reduced and the signal/noise (S/N) ratio deteriorates, because the collector-emitter breakdown voltage (BVCEO) is only 1V.3 This assumption was based on the fact that the product of fT and BVCEO is material-dependent, and Si-based devices such as SiGe HBT or CMOS transistors were about 200GHzV.
The limit of 200GHzV was proposed back in 1965, however; quite some time ago. This value was based on peak electron velocity and electric field which causes Si breakdown, but both values have changed considerably since then. In fact, some in the industry have expressed doubt as to the validity of the 200GHzV value in recent years.
Now, BVCEO has been raised to about 2V, "just barely within the level of possible commercialization," according to Maxim's Yamaguchi, and fT has been boosted. While the resulting device offers an absolute performance still inferior to InP technology, it is practical. "Calculation of the theoretical performance based on physical properties yields over 1 THzV," claims Katsuyoshi Washio, senior research scientist, ULSI Research Department, Central Research Laboratory, Hitachi Ltd. Many engineers agree with him, claiming that there is still considerable room for future improvement --not only SiGe engineers, but InP engineers as well.
Improvements in SiGe film growth process technology brought values closer to the theoretical limit. Technological competition among semiconductor manufacturers has driven the improvement of SiGe technology designed for 10-Gbit/s optical communication ICs and RF front-end ICs for cell phones and wireless LAN applications. One result of the competition is that the technology for forming low-defect films has almost been established, according to Teruhito Ohnishi, senior staff researcher, Advanced Technology Research Laboratories, Matsushita Electric Industrial Co, Ltd.
Boosting fMAX
If only fT is increased, then the benefits are only available to ICs processing digital signals, such as multiplexers and demultiplexers. If the maximum oscillation frequency (fMAX) can also be increased, it would provide a performance improvement for analog ICs, such as pre-amps, bandwidth-limited amps and voltage-controlled oscillators (VCO). Engineers want to increase integration levels in the chips, and so semiconductor engineers are working to solve two problems: increasing fMAX and increasing CMOS transistor integration density without sacrificing SiGe HBT performance.
A look at the performance of the devices announced at 2001 IEDM indicates that both fT and fMAX values are on the way up (Fig 3). Semiconductor manufacturers are looking to new transistor structures (Fig 4) minimizing parasitic resistance and capacitance, which makes it harder to boost fMAX. Instead of relying solely on lithography, they have adopted self-alignment technology with which finer line structures can be readily available.
An increase in fT for SiGe HBT can be accomplished by reducing the thickness of the base layer in the bipolar structure. If the thickness of the extrinsic base linking the base to the base electrode is also reduced, then resistance between base and base electrode (called the base resistance) rises. The value of fMAX will rise with fT, but because base resistance also increases, a cap is imposed on fMAX improvement.
The base resistance can be easily dropped by making the extrinsic base thick. Conexant reduced base resistance by embedding p+ layer into the extrinsic base, achieving the best to date SiGe HBT with an fT of 200GHz and an fMAX of 180GHz. The firm claims that further thinning of dimensions will boost both values over 200GHz.
Parasitic Capacitance
Hitachi's process is to form a thicker extrinsic base before the base layer formation. Their approach is effective in reducing parasitic capacitance, and while the Hitachi prototype SiGe HBT slashes both parasitic resistance and parasitic capacitance to achieve an fT of 124GHz (lower than Conexant's achievement), fMAX is relatively high at 174GHz.4 Parasitic capacitance is lowered because the emitter and collector regions are about the same size, decreasing the overlap region.
Technologies for integrating an analog SiGe HBT front-end circuit with baseband circuit, digital signal processors (DSP) and other digital CMOS circuits also demonstrated progress at 2001 IEDM. One especially eye-catching presentation was Hitachi's SiGeC technology, which adds carbon to SiGe. Carbon acts to relieve distortion in the SiGe, boosting the breakdown voltage.
When SiGe HBT and CMOS transistors are integrated, the SiGe HBT is first formed, and then heat treatment is used to activate the n- and p-type dopants in CMOS transistor sources and drains. Temperatures reach 1,000Centigrade, which can degrade SiGe HBT characteristics.
When carbon is added to the base SiGe layer it restrains the dispersion of boron (base dopant) into the bipolar transistor emitter and collector, maintaining a high boron concentration in the base, and providing an increase of about 25% in fT and fMAX.
Finer-Line MOS
The performance of MOS technology is also improving. Fujitsu Laboratories Ltd announced an nMOS transistor with an fMAX of 185GHz -- double the previous high -- at IEDM 2001.5 While the fT of 120GHz is still inferior to that of SiGe HBT (200GHz), fMAX is better by 5GHz.
According to the International Technology Roadmap for Semiconductors (ITRS), which defines future performance demands for CMOS technology, practical MOS transistors with an fMAX of 185GHz are not expected until 2016. According to Toshihiro Sugii, director, Advanced Device Department, C Project Group, Fujitsu Laboratories, "We can use the process technology of logic ICs, and we will be able to make Bi-CMOS ICs with the same process count."
If MOS transistors achieve an fT of 200GHz, on a par with existing SiGe HBT, it would mean a gate length of about 50nm, equivalent to cutting-edge technology slated for implementation in microprocessors in 2005. Within three years, it would be a proven volume-production technology. However, MOS transistors would suffer from variation in electrical characteristics, which grows more severe as geometry shrinks, and as a result, some in the industry feel that advanced logic IC processes will not be applicable to analog signal processing ICs.
Reducing Rgate, Cparas
CMOS technology has always increased transistor operating speed by reducing geometry, and fT has steadily risen apace.
The situation is different for fMAX, though. Shrinking dimensions mean shorter gate lengths and therefore faster transistor switching, but at the same time gate resistance rises, making it harder to boost fMAX. The situation is the same with SiGe HBT, where thinning the base to boost fT results in higher base resistance and imposes a ceiling on fMAX.
Fujitsu Laboratories has three methods to increase fMAX in its MOS transistors, namely: (1) reducing gate resistance by adding metal on top of the gate electrode; (2) using dynamic-threshold MOS (DTMOS) to shorten the gate and the substrate, boosting fT ; and, (3) using totally-depleted silicon-on-insulator (SOI) wafers to minimize parasitic capacitance.
Of these, the metal deposition on the gate electrode was the most effective. An Al coating slashed gate resistance by 1/200th. Compared to a design without the Al metallization, fMAX is about three times higher.
Mixed Signal Circuits
At 2001 IEDM, Mitsubishi Electric Corp used a different approach to improve fMAX, achieving a respectable 135GHz6, although it was less than what has been achieved by Fujitsu Laboratories. The firm focused on slashing parasitic capacitance between gate and drain, and between gate and source (Fig 5). Mitsubishi's approach is to single-chip logic and analog signal processing, optimizing overlapped regions of a source and drain under the gate dielectric layer to match each circuit.
For example, source and drain areas are made larger for logic circuits, which are less susceptible to parasitic capacitance, reducing the distance between the source and drain to boost operating speed. The opposite approach is used in circuits with analog signal processing.
by Satoshi Okubo
Websites:
Conexant Systems: http://www.conexant.com
Fujitsu Laboratories: http://www.labs.fujitsu.com/en
Hitachi: http://global.hitachi.com
IBM: http://www.ibm.com
Matsushita Electric Industrial: http://www.panasonic.co.jp/global
Mitsubishi Electric: http://www.mitsubishielectric.com
References:
1) Jeng, S. J, et al, "A 210-GHz fT SiGe HBT With a Non-Self-Aligned Structure," IEEE Electron Device Letters, pp 542-544, Nov 2001.
2) Racanelli, M, et al, "Ultra High Speed SiGe NPN for Advanced BiCMOS Technology," 2001 International Electron Devices Meeting Technical Digest, pp 336-339, Dec 2001.
3) Kato, M, Yomogita, H and Ookubo, S, "Bluetooth Expedites Moves for CMOS RF Chip," pp 46-51, vol 10, no 6, Nikkei Electronics Asia, June 2001.
4) Oda, K, et al, "Self-Aligned Selective-Epitaxial-Growth Si1-x-y GexCy HBT Technology Featuring 170-GHz fMAX ," 2001 International Electron Devices Meeting Technical Digest, pp 332-335, Dec 2001.
5) Hirose, T, et al, "A 185-GHz fMAX SOI DTMOS with A New Metallic Overlaygate for Low-power RF Applications," ibid, pp 943-945, Dec 2001.
6) Matsumoto, T, et al, "70nm SOI-CMOS of 135-GHz fMAX with Dual OffsetImplanted Source-Drain Extension Structure for RF/Analog and Logic Applications," ibid, pp 219-222, Dec 2001.
(April 2002 Issue, Nikkei Electronics Asia)
